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/**
 * \file Buffer_sve.cpp
 * \brief SVE implementation of buffer operations.
 */
//  ====================================================================================================================
//  Includes
//  ====================================================================================================================

#include "CommonLib/Buffer.h"
#include "CommonLib/CommonDef.h"
#include "CommonLib/arm/CommonDefARM.h"

//! \ingroup CommonLib
//! \{

#if defined( TARGET_SIMD_ARM_SVE ) && ENABLE_SIMD_OPT_BUFFER

#include "CommonLib/arm/sve/tbl_sve.h"

namespace vvdec
{

void rspFwdCore_sve( Pel* ptr, ptrdiff_t ptrStride, int width, int height, const int bd, const Pel OrgCW,
                     const Pel* LmcsPivot, const Pel* ScaleCoeff, const Pel* InputPivot )
{
  CHECKD( svcnth() < 16, "rspFwdCore_sve expects at least 16 halfword (256-bit) SVE vector length, but svcnth() == " << svcnth() );

  int shift = getLog2( OrgCW );

  const svbool_t p = svptrue_pat_b16( SV_VL16 );
  const svint16_t mLmcsPivot = svld1_s16( p, LmcsPivot );
  const svint16_t mInputPivot = svld1_s16( p, InputPivot );
  const svint16_t mScaleCoeff = svld1_s16( p, ScaleCoeff );

  const int16x8_t mMin = vdupq_n_s16( 0 );
  const int16x8_t mMax = vdupq_n_s16( ( 1 << bd ) - 1 );

  if( ( width & 7 ) == 0 )
  {
    do
    {
      int w = 0;
      do
      {
        const int16x8_t xsrc = vld1q_s16( &ptr[w] );

        // ( idxY = ptr[w] >> shift ) range is [0, 15].
        uint16x8_t idxY = vreinterpretq_u16_s16( vshlq_s16( xsrc, vdupq_n_s16( -shift ) ) );

        const int16x8_t xlmc = vvdec_svtbl_s16( mLmcsPivot, idxY );
        const int16x8_t xinp = vvdec_svtbl_s16( mInputPivot, idxY );
        const int16x8_t xscl = vvdec_svtbl_s16( mScaleCoeff, idxY );

        int16x8_t diff = vqsubq_s16( xsrc, xinp );

        // vqrdmlahq uses Q15 rounding: (a * b) >> 15. We need (diff * xscl) >> 11,
        // so pre-scale diff by 2^4 to make (diff << 4) * xscl >> 15 == diff * xscl >> 11.
        int16x8_t diff_shift4 = vshlq_n_s16( diff, 4 );
        int16x8_t xtmp1 = vqrdmlahq_s16( xlmc, diff_shift4, xscl );

        xtmp1 = vminq_s16( xtmp1, mMax );
        xtmp1 = vmaxq_s16( xtmp1, mMin );

        vst1q_s16( &ptr[w], xtmp1 );

        w += 8;
      } while( w < width );
      ptr += ptrStride;
    } while( --height != 0 );
  }
  else // width == 4
  {
    CHECKD( width != 4, "rspFwdCore_sve else path expects width == 4" );

    do
    {
      const int16x4_t xsrc = vld1_s16( ptr );

      // ( idxY = ptr[w] >> shift ) range is [0, 15].
      uint16x4_t idxY_half = vreinterpret_u16_s16( vshl_s16( xsrc, vdup_n_s16( -shift ) ) );
      uint16x8_t idxY = vcombine_u16( idxY_half, vdup_n_u16( 0 ) );

      const int16x4_t xlmc = vget_low_s16( vvdec_svtbl_s16( mLmcsPivot, idxY ) );
      const int16x4_t xinp = vget_low_s16( vvdec_svtbl_s16( mInputPivot, idxY ) );
      const int16x4_t xscl = vget_low_s16( vvdec_svtbl_s16( mScaleCoeff, idxY ) );

      int16x4_t diff = vqsub_s16( xsrc, xinp );

      // vqrdmlah uses Q15 rounding: (a * b) >> 15. We need (diff * xscl) >> 11,
      // so pre-scale diff by 2^4 to make (diff << 4) * xscl >> 15 == diff * xscl >> 11.
      int16x4_t diff_shift4 = vshl_n_s16( diff, 4 );
      int16x4_t xtmp1 = vqrdmlah_s16( xlmc, diff_shift4, xscl );

      xtmp1 = vmin_s16( xtmp1, vget_low_s16( mMax ) );
      xtmp1 = vmax_s16( xtmp1, vget_low_s16( mMin ) );

      vst1_s16( ptr, xtmp1 );

      ptr += ptrStride;
    } while( --height != 0 );
  }
}

template<>
void PelBufferOps::_initPelBufOpsARM<SVE>()
{
  // Enable only if the CPU supports at least 16 halfword (256-bit) SVE vectors.
  if( svcnth() >= 16 )
  {
    rspFwd = rspFwdCore_sve;
  }
}

} // namespace vvdec

#endif // defined( TARGET_SIMD_ARM_SVE ) && ENABLE_SIMD_OPT_BUFFER

//! \}
